The invention relates to an integration circuit and an integration method and, more particularly, to an improvement thereto in that an integrated output signal is sustained at a correct value.
An integration circuit, which integrates an input signal to produce an integrated signal, is well-known and used as an analogue to digital converter, for example. One such integration circuits is shown in FIG. 1. In the figure, an operational amplifier designated by reference numeral 2 has two input terminals, i.e. inverting and non-inverting, terminals and an output terminal. The non-inverting terminal is connected to a reference voltage source 4 supplying a voltage V.sub.A, for example, the ground potential. An integration capacitor 6 with a capacitance C is inserted between the inverting terminal and the output terminal of the operational amplifier 2. The inverting terminal is further connected to one end of an integration resistor 8 with a resistance R. The resistor 8 is connected at the other end to a voltage source 12 for supplying a voltage Vs to be integrated, through a switch 10. The open and close operations of the switch 10 are controlled by a control signal supplied from a control voltage signal source (Vc) 14. FIGS. 2A to 2C illustrate waveforms of signals at points a, b and c in the circuit in FIG. 1, respectively. The switch 10 is closed when the control voltage signal Vc is at high level (during the period from t.sub.1 to t.sub.2), for example. The voltage signal Vs is continuously applied to the other end of the resistor 8 so long as the switch 10 is closed. The potential at the inverting terminal of the amplifier 2 when the switch 10 is open is equal to that at the non-inverting terminal.
FIG. 2B shows a signal waveform illustrating a potential change at said other end of the resistor 8, i.e. the terminal at the voltage source 12 side. When the voltage signal Vs to be integrated is applied to said other end of the resistor 8 during the period from t.sub.1 to t.sub.2, as shown in FIG. 2B, an integrated output signal having a value V.sub.02 appears at time t.sub.2 at the output terminal of the amplifier 2, as shown in FIG. 2C. The signal V.sub.02 is given ##EQU1## where V.sub.01 is the potential at the output terminal of the amplifier 2, at time t.sub.1. When the switch 10 is opened at time t.sub.2, the potential at said other end of the resistor 8 instantaneously returns to the reference potential V.sub.A, as indicated by a solid line in FIG. 2B. Therefore, the potential at the output terminal, i.e. the point c, must be fixed at the integrated value V.sub.02 after time t.sub.2, as indicated by a solid line in FIG. 2C.
However, the potential at said other end of the resistor 8, in fact, does not sharply reduce to the reference potential V.sub.A at time t.sub.2 but starts at time t.sub.2 to exponentially decrease and to be equal to the reference potential V.sub.A at time t.sub.3. Thus, the potential of the signal at the output terminal, or the point c, of the amplifier 2 continues its change after time t.sub.2 and stops it at time t.sub.3 to be constant. As a result, the output signal at the output terminal of the amplifier includes an integration value of the input signal taken from time t.sub.1 to t.sub.2 and another integration value of the potential change from time t.sub.2 to t.sub.3 at said other end of the resistor 8. As described above, in the integration circuit shown in FIG. 1, the potential of the integrated output signal at the output terminal of the amplifier 2 does not have a correct value, V.sub.02. This is distinguished particularly when an analogue switch formed by a metal oxide semiconductor transistor is used for the switch 10. The inventors of the present application studied the cause of the integrated output signal having an improper value, i.e. why the potential at said other end of the resistor 8 does not instantaneously change to the potential V.sub.A at the same time as the switch 10 is opened but exponentially changes to the potential V.sub.A. As a result of this study, it is found that the switch 10 in the integration circuit has a parasitic capacitance 16 and that, when the voltage signal to be integrated is applied to said other terminal of the resistor 8, charges are stored in the parasitic capacitor 16 and, when the switch 10 is opened, the charges are discharged through the resistor 8. That is to say, this fact causes the integrated signal to be improper in value.
The present invention, which is based on this fact, applies a reference voltage to said other end (the point b) of the resistor 8 in the same instance that the switch 10 is opened, thereby to block the flow of the charges stored in the parasitic capacitor 16 through the resistor 8.